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Hardware · Spectrum ML · Neuromorphic

Research & Innovation

From cognitive radio and federated spectrum sensing to FPGA/ASIC bring-up, FinFET clocking, and spiking models mapped to hardware—ideas grounded in measurement, EDA practice, and peer-reviewed publication.

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Explore focus areas View active projects Publications

Research areas

Four pillars tied to UMBC work, internships, and publications—cognitive radio ML, silicon/EDA practice, and neuromorphic acceleration.

Cognitive radio & spectrum ML

Interweave / underlay detection, spiking and federated models for white-space sensing, and communications-aware evaluation on constrained hardware.

ASIC / FPGA & EDA

RTL-to-GDSII mindset, timing and power trade-offs, FPGA HLS bring-up, and internship-scale verification on display and SoC paths.

Neuromorphic & edge ML

Mapping SNN and spectral–temporal models to accelerators and edge targets with reproducible datasets and clear baselines.

Robust circuits & prior silicon work

Earlier Kyung Hee work on radiation effects, SRAM, and tape-out informed how I reason about fault mechanisms and margin.

Current projects

Active threads at the Ph.D. stage—spectrum intelligence, federated edge sensing, and reliable digital implementation paths.

Focus

Ongoing Funded

Federated and transformer-based spectrum detectors

Extending ICC / TCCN lines on lightweight federated and autoencoder–transformer detectors for interweave cognitive radios and vehicular settings.

Cognitive radio Federated learning

Past projects

Course and research projects spanning UMBC (2021–2022), Kyung Hee University (2013–2015), and volunteer work—hardware, ML, EDA, and radiation-hardened silicon.

Capstone

FPGA Realization of a Spiking Neural Network Model for Opportunistic Spectrum Access

UMBC course project, Sep–Dec 2022. Report

FPGA SNN
Capstone

Human Physical Activity Recognition Using Stacked Long Short-Term Memory

UMBC course project, Sep–Dec 2022. Report

LSTM Activity recognition
Capstone

Analysis of Branch Prediction Strategies

UMBC course project, Feb–May 2022. Report

CPU arch Microarchitecture
Capstone

Comparison of Deep Neural Network Implementations in FPGA and ASIC

UMBC course project, Sep–Dec 2021. Report

FPGA ASIC DNN
Capstone

Hardware-Software Co-design for the Gaussian Naive Bayes Method Using SystemC and SystemVerilog

UMBC course project, Sep–Dec 2021. Report

SystemC SystemVerilog
Capstone

64-Byte Cache Design Using VHDL and Layout Design Using 0.6 µm Planar Technology

UMBC course project, Feb–May 2021. Report

VHDL Layout
Capstone

Demonstration of a Center-Out Reaching Task Using Virtual Reality (VR Builder–Simulink)

UMBC course project, Feb–May 2021. Report

VR Simulink
Capstone

Multi-Cycle Microprocessor Without Interlocked Pipeline Stages (Samsung 180 nm PDK)

RTL, verification, and physical design flow on a commercial PDK. KHU, Feb–May 2014.

MIPS-style PDK RTL
Capstone

TID Effect on Cache Memory (SRAM) — 28 nm FD-SOI Tape-Out

Total ionizing dose characterization of SRAM standby power under radiation. KHU CSA & VLSI Lab, Aug 2013–Aug 2015. Led to IEEE Trans. Nuclear Science publication (2015).

SRAM TID Radiation hardening 28nm FD-SOI
Capstone

Radiation Effect on Standby Power of SRAM — 28 nm FD-SOI Tape-Out

Supply voltage decision methodology to minimize SRAM standby power under radiation environment. KHU CSA & VLSI Lab, Jun 2013–Aug 2015.

SRAM Standby power Radiation hardening Voltage scaling
Capstone

Radiation Effect in Combinational Circuits — 28 nm FD-SOI Tape-Out

Single-event and TID effects on combinational logic reliability. KHU CSA & VLSI Lab, May 2013–Aug 2015.

Combinational circuits Radiation effects 28nm FD-SOI
Capstone

Robust Flip-Flop Design to Mitigate Single-Event Upset — 130 nm HCOMS9SOI Tape-Out

Radiation-hardened flip-flop cell verified under nuclear radiation at KIRAMS. KHU CSA & VLSI Lab, Mar 2013–Aug 2015.

Flip-flop SEU Radiation hardening 130nm
Capstone

Mortality Rate Analysis for Local Insurance Company

Volunteer data analysis project for Padma Islami Life Insurance Ltd., Dhaka. Jul 2009–Feb 2013.

Data analysis Statistics Insurance
Capstone

Microcontroller-Based Power Factor Meter (PIC 16F877)

Volunteer hardware project; designed and built a PF meter using PIC 16F877 microcontroller. Jan–Aug 2008.

Microcontroller PIC16F877 Power factor

Training & workshop

Formal industry training and short courses—PLC, power systems, FACTS, and hands-on digital design.

Programmable Logic Controller (PLC)

Six months of training on programmable logic controllers, organized bySystem Engineering Limited.

Certificate

Third Generation FACTS Devices

Short course on "Third Generation FACTS Devices: Dynamic Modeling and Simulation."

Certificate

FPGA prototyping & design flow

Hands-on workshop covering RTL synthesis, timing constraints, and bitstream bring-up on commercial FPGA boards.

Power electronics fundamentals

Short course on DC–DC converters, magnetics basics, and simulation-led design practice for switching supplies.

Research timeline

Milestones from early tape-out silicon (2013–2015) through Elsevier journals (2018) and Ph.D.-stage spectrum ML (2022–2025)—pair with publications for detail.

  • 2025

    ICC cognitive radio detectors & vehicular extensions

    IEEE ICC papers on ATIC (autoencoder–transformer) and lightweight spiking federated detectors.

  • 2024

    GLOBECOM spectrum sensing & ICC SNN demodulation

    White-space detectors and optoacoustic demodulation using spiking neural network structures.

  • 2024

    IEEE TCCN: spectral–temporal opportunistic spectrum access

    Archival journal model for cognitive radio channel availability with co-authors at UMBC.

  • 2022

    ISCAS FinFET resonant clocking

    Conference and arXiv report on power/skew reduction in 14-nm FinFET clock networks.

  • 2018

    Elsevier journal papers — power systems & control

    Franklin Institute (Elsevier) publication on susceptance variation and lead–lag control for grid-connected FSIG wind generators; ISA Transactions (Elsevier) paper on GUPFC-equipped single-machine infinite bus system for low-frequency oscillation damping.

  • 2015

    IEEE Trans. Nuclear Science & KHU tape-out work

    Three tape-out chips at Kyung Hee University (28 nm FD-SOI and 130 nm HCOMS9SOI): SRAM standby power under radiation, combinational circuit radiation effects, and SEU-mitigating flip-flop design—verified at KIRAMS under nuclear radiation conditions. SRAM work published in IEEE Transactions on Nuclear Science, vol. 62, no. 3 (2015).

  • 2013

    Springer Journal of Electronic Materials — ultrathin solar cell study

    Co-authored archival paper in Journal of Electronic Materials (Springer), vol. 42, no. 10, pp. 2867–2875, on III–V compound paths toward high efficiency in ultrathin-film solar cells—alongside the Kyung Hee University microelectronics and VLSI research line. DOI: 10.1007/s11664-013-2659-z.

Research interests

Keywords spanning publications, coursework, and lab practice.

Cognitive radio Spectrum sensing Spiking neural networks Federated learning FPGA prototyping ASIC / EDA flows FinFET / low-power digital Radiation hardening (prior work) Edge ML Hardware verification PyTorch on embedded targets Technical writing Reproducible experiments Teaching–research bridges

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Hardware research should be falsifiable: simulate, prototype, measure—and publish with enough detail for the next builder to continue.