EDA & ASIC / FPGA
Flows, verification, and platform bring-up for complex designs—from specification to tape-out mindset.
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Researcher · Hardware Engineer · Educator
Ph.D. in Computer Engineering (Dec 2025) — University of Maryland Baltimore County (UMBC)
I work at the intersection of EDA, ASIC/FPGA systems, and edge & neuromorphic ML—building reliable hardware flows and translating research into teaching and collaboration. Browse the sections below or jump straight to biography and research.
Snapshot
Quick metrics across research, publications, collaborations, and engineering experience.
Focus
High-level themes that show up across research, teaching, and engineering practice.
Flows, verification, and platform bring-up for complex designs—from specification to tape-out mindset.
See researchEfficient inference, accelerators, and communication-aware hardware where reliability meets constraints.
View publicationsClear explanations, honest feedback, and projects students can show in portfolios and interviews.
Teaching pageResearch visits, internships, and industry-aligned projects with concrete deliverables.
Get in touchShip with evidence, learn in public, and leave the codebase—and the silicon mindset—kinder than you found it.
Path
Degrees and institutions—see Biography for transcripts, dates, and full narrative.
Computer Engineering — doctoral program completed Dec 2025; cognitive radio ML, FPGA/ASIC, and neuromorphic themes.
Computer engineering (UMBC) and electronics/radio engineering (Kyung Hee); CGPA 3.97 / 4.00 and 4.10 / 4.30 respectively.
Electrical & electronic engineering — core math, circuits, and systems.
Experience
A concise view of current and recent roles—full narrative, dates, and CV-style detail live on Biography.
University of Maryland Baltimore County
GTA/GRA work across architecture, image processing, circuits & ML labs, and PLD; GRAs on FPGA partial reconfiguration, FinFET layout, HLS SNNs, PyTorch modulation for multipath, LTE white-space detection, and related reporting. Degree completed Dec 2025 (CGPA 3.97/4.00).
Jan 2021 – Dec 2025
Meta Reality Labs
Summer 2024 on-site (Redmond): AR/VR FPGA prototyping for laser/LCoS micro-display controllers—RTL & HLS IPs, micro-arch and verification reviews, SWaP-C analysis, and verification infrastructure.
May 2024 – Aug 2024
Lasarrus Clinic & Research Center
WearME FPGA prototype for COPD patients—RTL + C/C++ on Altera SoC DE10-nano; ADC/DAC interfaces; PLL design; deep learning algorithms; FDA-compliant documentation (hybrid role).
Aug 2023 – Mar 2024
Intel Corporation
Next-generation Xeon SoC: high-speed clock distribution—skew, jitter, latency; static timing analysis, ANOVA simulation, power/variation analysis. Synopsys Fusion Compiler, ICC II, Cadence Virtuoso—remote Hudson, MA.
May 2022 – May 2023
Skills
Grouped by how they show up in research, hardware work, and teaching—not an exhaustive keyword dump.
RTL, verification, and bring-up
Efficient inference & accelerators
Shipping reliable platforms
Classroom, docs, and mentorship
Extracurricular
Skills and certifications from Coursera, Udemy, HackerRank, and similar platforms—beyond formal degree coursework. Hover to reveal details and open the related page.
Projects
Three active efforts across embedded systems, AI / ML, and research-to-practice tooling.
ICC / GLOBECOM / TCCN thread on lightweight federated and spiking neural detectors for white-space and vehicular cognitive radio settings.
ISCAS work (with collaborators) on resonant energy recycling for 14-nm FinFET clocks—extended arXiv report.
Lasarrus internship: FPGA-centric prototype path integrating DL models with CAD and simulation-driven validation.
Publications
A quick look at recent publication highlights across hardware systems, edge intelligence, and reliable engineering practice.
Interweave cognitive communications journal extension building on UMBC spectrum ML work with Mohamed F. Younis.
Archival cognitive radio model with Brian W. Stevens and Mohamed F. Younis—foundation for later ICC/GLOBECOM detectors.
Conference detector with Tasnim Nishat Islam—autoencoder + transformer pipeline for interweave sensing.
Volunteering
Selected volunteer contributions in mentoring, technical community support, and academic outreach.
IEEE & archival venues
Peer review for wireless, communications, and related hardware venues—supporting rigorous, constructive feedback cycles.
Ongoing
Student projects
Office hours and project guidance across FPGA, ML, and architecture labs—emphasis on reproducible experiments and clear write-ups.
2021 – Present
IUT IEEE Chapter
Organized industrial training visits, project exhibitions, and workshops for EEE department students at Islamic University of Technology.
Oct 2011 – Oct 2012
ORCA & Esonance
Member of ORCA (Old Rajshahi Cadets' Association)—blood donation drives and fundraising. Editorial board member for "Amber" magazine at Esonance (IUT EEE department annual fest).
2011 – 2020
Recommendations
Professional recommendations from LinkedIn—internship mentors, managers, instructors, and long-term collaborators.
Recognition
Selected recognitions from research, innovation, mentorship, and academic excellence.
Government of South Korea — Master's research at Kyung Hee University (CSA & VLSI Lab).
Organisation of Islamic Cooperation — undergraduate entry at Islamic University of Technology.
Bangladesh Education Board — for excellent higher-secondary results (Rajshahi Cadet College).
Bangladesh Education Board — for excellent secondary-school results.
Explore
Quick links to the rest of the site—use this as a map after the story and highlights above.
Research questions, hardware collaborations, or teaching—send a message and we’ll find a path.
More
Commands, demos, and Mehedi Bot—without leaving the browser.
Résumé-style commands, themes, weather, and a few surprises—keyboard-first.
Open terminalFull publication list and citation graph live on Google Scholar—linked from publications.
Publications hubBased in Baltimore, Maryland, USA (Eastern Time)—map and contact details on the contact page.
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