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Biography

Mehedi Hasan Galib

Researcher · Hardware Engineer · Educator

I work at the intersection of cognitive radio / spectrum ML, FPGA and ASIC bring-up, and neuromorphic edge intelligence—grounded in peer-reviewed publication, industry internships, and years of teaching labs.

Full biography

I am Md Mehedi Hassan Galib, a computer engineer working across cognitive radio and spectrum machine learning, FPGA/ASIC design flows, and neuromorphic / edge inference. My Ph.D. at UMBC (completed Dec 2025) focused on communications-oriented hardware research with a strong publication record in IEEE TCCN, ICC, and GLOBECOM.
Industry internships at Meta Reality Labs, Intel, and Lasarrus sharpened RTL/HLS practice, verification discipline, and SWaP-aware prototyping—from micro-display controllers to SoC clocking and wearable FPGA systems. Graduate assistantships blended GRA threads (partial reconfiguration, FinFET layout, HLS SNNs, LTE white-space detection) with GTA roles across architecture, image processing, circuits & ML labs, and PLD courses.
Earlier chapters include a Master’s at Kyung Hee University on radiation-oriented silicon topics, faculty teaching at IUT, and foundational training at Rajshahi Cadet College. I care about clarity: measured claims, reproducible experiments, and teaching that helps students explain what they built—not only that it runs.

“Ship with evidence, learn in public, and leave the codebase kinder than you found it.”

— Working principles

Education

Ph.D. in Computer Engineering (UMBC · Dec 2025)

University of Maryland Baltimore County, USA

CGPA 3.97 / 4.00

MSc. in Computer Engineering

University of Maryland Baltimore County, USA

CGPA 3.97 / 4.00

MSc. in Electronics and Radio Engineering

Kyung Hee University, South Korea

CGPA 4.10 / 4.30

BSc. in Electrical and Electronic Engineering

Islamic University of Technology, Dhaka, Bangladesh

CGPA 3.98 / 4.00

Career timeline

Career Timeline

Graduate Teaching & Research Assistant @ UMBC

Jan 2021 – Dec 2025 · Baltimore, MD · On-site / Remote

During the Ph.D. (completed Dec 2025), multiple GTA/GRA appointments—computer architecture (CMPE/CMSC 611), digital image processing (ENEE/CMSC 691), circuits & ML labs (CMPE 306/678), PLD & electronics (CMPE 415/314). GRAs: Xilinx DPR & FinFET layout, HLS spike neural nets, bio-inspired architectures, PyTorch modulation for multipath/edge, LTE whitespace detection, and related reporting.

University of Maryland Baltimore County, USA

ASIC/FPGA Hardware Engineer Intern · Meta Reality Labs

May 2024 – Aug 2024 · 4 months

AR/VR rapid FPGA prototyping for laser/LCoS micro-display controllers; RTL & HLS IPs, micro-arch and verification reviews, SWaP-C analysis, and verification infrastructure—true-color RGB on micro-display.

Redmond, Washington, USA · On-site

FPGA & ASIC Engineer Intern · Lasarrus Clinic and Research Center

Aug 2023 – Mar 2024 · 8 months

FPGA-based prototype of the WearME device for COPD patients—RTL + C/C++ on Altera SoC DE10-nano; ADC/DAC interfaces; EMI/ESI reduction; PLL design; deep learning algorithms; PCB design; FDA-compliant documentation. Xilinx Vivado, Altera Quartus.

Hybrid

Graduate Technical Intern · Intel Corporation

May 2022 – May 2023 · 1 year 1 month

Next-generation Xeon SoC: high-speed clock distribution with optimized skew, jitter, and latency. Static timing analysis, ANOVA simulation, power analysis, and global variation analysis—Synopsys Fusion Compiler, ICC II, Cadence Virtuoso; Python, MATLAB, Excel.

Hudson, Massachusetts, USA · Remote

Assistant Professor & Lecturer · Islamic University of Technology

Aug 2016 – Jan 2021 · Gazipur · On-site

Assistant Professor: numerical methods theory & lab. Lecturer: semiconductor devices, advanced electronics, VLSI, digital electronics, microprocessors, signals & systems, AC circuits—labs with Python, MATLAB, CAD, LabVIEW, Simulink.

Gazipur District, Bangladesh

Graduate Research Assistant · Kyung Hee University (CSA & VLSI Lab)

Feb 2013 – Aug 2015 · Full-time

TID effects on SRAM cache (28nm FD SOI tape-out); radiation-hardened combinational logic & flip-flops; robust FF against SEU (130nm tape-out)—literature, simulation (Eldo), layout, and chip verification under radiation.

Yongin, Gyeonggi, South Korea

Faculty Member (Part-time) · Ahsanullah University of Science and Technology

Nov 2012 – Jan 2013 · 3 months

Conducted Digital System Design laboratory sessions.

Dhaka, Bangladesh

Data Analyst Intern · Padma Islami Life Insurance

Sep 2009 – Jun 2010 · 10 months

Data analysis workflows using Python.

Dhaka, Bangladesh · Hybrid

Professional summary

Technical experience

  • 12+ years of experience in EDA/silicon development tools, including Cadence, Synopsys, and Mentor Graphics.
  • 12+ years of experience in programming languages, including Matlab, Python, C, and C++.
  • 10+ years of experience in HDL languages, including Verilog, System Verilog, and System C.
  • 10+ years of experience designing low-power, energy-efficient systems, optimizing trade-offs between performance, power, and area.
  • 10+ years of experience in both full custom and semi-custom ASIC design flow, covering all stages from RTL to GDSII.
  • 5+ years of experience with machine learning tools on CPU, GPU, and Raspberry Pi; targeting resource-constrained edge devices.
  • 4+ years of experience in neuromorphic computing, spiking neural networks, and Hebbian learning.
  • 3+ years of experience in computer architecture concepts: microprocessor architecture, memory systems, on-chip interconnection networks, and hardware/software partitioning.

Strengths & collaboration

  • Results-oriented, self-motivated, and proactive, with demonstrated creative and critical thinking capabilities.
  • Skilled in technical writing; write, understand, and follow standard operating procedures (SOPs).
  • Experienced in collaborating and leading in a team environment.

Technical skills

EDA / CAD tools

Cadence Spectre Cadence Virtuoso Cadence SoC Encounter Cadence Innovus Mentor Graphics Calibre Synopsys Fusion Compiler Synopsys VCS Synopsys Design Compiler Synopsys ICC II Synopsys Prime-time Synopsys Prime-power Synopsys Platform Architect

FPGA platform

Xilinx Vitis HLS Xilinx Vivado Altera Quartus Altera Modelsim NIOS

Machine learning

PyTorch TensorFlow Scikit-learn Keras Pandas Matplotlib CUDA HPC (MPI)

Languages

Python C C++ Assembly NodeJS R

Script & sim

Perl TCL Eldo HSpice PSpice Make Linux OS Shell (bash)

HDL

Verilog System Verilog VHDL System C

Debug & verification

ELVIS board Oscilloscope Logic Analyzer UVM

Microcontrollers

Raspberry Pi Arduino Atmel (8051 AVR32) Microchip (pic16 pic32)

Engineering software

Matlab MPLab Proteus Windmil HP Labs-CACTI cache simulator

Applications

MS Office Word Excel PowerPoint Visio LaTeX Figma Canva

Version control

GitHub SVN BitBucket

Web

HTML CSS JavaScript React

Soft skills

Leadership Adaptability Communication Goal-oriented Problem-solving Technical writing

Awards & honors

Brain Korea Scholarship

Government of South Korea · Jan 2014

Kyung Hee University · CSA & VLSI Lab

Excellent performance in Master's research work.

2014

OIC scholarship

Organisation of Islamic Cooperation · Dec 2008

Islamic University of Technology

Excellent performance at Islamic University of Technology's entrance exam for the undergraduate program.

2008

Government scholarship for H.S.C result

Bangladesh Education Board · Dec 2008

Rajshahi Cadet College

For excellent result in H.S.C.

2008

Government scholarship for S.S.C result

Bangladesh Education Board · Sep 2006

Rajshahi Cadet College

For excellent result in S.S.C.

2006

Curriculum vitae

Upload a PDF on the CV section row, or keep a file at documents/cv.pdf under static files as fallback.