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Research · Teaching · Practice

Impact beyond the paper

Peer-reviewed hardware and communications research, multi-year teaching assistantships, and industry internships that informed how ideas are scoped, measured, and handed off to collaborators.

0 Peer-reviewed publications
0 IEEE archival venues
0 Years teaching & mentoring
0 Industry internships

Real-World Impact of Research

Research translated into outcomes

Cognitive radio & spectrum ML

Spectral-temporal modeling for opportunistic spectrum access published in IEEE Transactions on Cognitive Communications and Networking (vol. 10, no. 2, Apr 2024). Extended threads on spiking neural network-based and federated learning-based white-space detectors accepted at IEEE ICC 2024 (Cognitive Radio and AI-Enabled Networks) and submitted to IEEE GLOBECOM 2024 (Cognitive Radio and IoT & Sensor Networks tracks).

  • Beneficiaries: Wireless research community & cognitive radio collaborators
  • Outcome: Reproducible SNN and federated detector baselines with documented channel assumptions
  • Metric: IEEE TCCN journal + ICC & GLOBECOM conference track record

Silicon-minded hardware design

Radiation-hardened SRAM and flip-flop tape-out chips (28 nm FD-SOI, 130 nm HCOMS9SOI) at Kyung Hee University led to an IEEE Transactions on Nuclear Science journal paper (2015). FinFET clock-network work on power and skew reduction using resonant energy recycling published at IEEE ISCAS 2022. Industry internships at Meta Reality Labs (LCoS laser controller for AR/VR micro-display), Intel (Xeon SoC high-speed clock distribution), and Lasarrus Clinic (WearME FPGA prototype for COPD patients) translate RTL-to-silicon discipline into production settings.

  • Beneficiaries: Chip design teams, hardware researchers, and FPGA/ASIC engineers
  • Outcome: Tape-out verified radiation-hardened cells and industry-grade FPGA/SoC prototypes
  • Metric: IEEE Trans. Nuclear Science + IEEE ISCAS + Meta / Intel / Lasarrus deliverables

Teaching & mentorship footprint

Four-and-a-half years as faculty at Islamic University of Technology (Lecturer 2016–2019, Assistant Professor 2019–2021) teaching VLSI circuits, semiconductor devices, advanced electronics, and microprocessor lab courses. Since 2021, UMBC graduate TAships spanning Advanced Computer Architecture (CMPE/CMSC 611), Advanced Machine Learning (CMPE 678), Digital Image Processing (ENEE 612), Programmable Logic Devices (CMPE 415), and Introductory Circuit Theory (CMPE 306).

  • Beneficiaries: Undergraduate and graduate engineering students across two continents
  • Outcome: Structured lab supervision, reproducible course materials, and graded feedback cycles
  • Metric: 10+ years of classroom and lab instruction across UMBC and IUT

Numerical methods & computational modeling

Analytical models across the publication record — spectral-temporal channel distributions (IEEE TCCN 2024), supply-voltage leakage minimization (IEEE TNS 2015), and lead-lag power-system optimization (J. Franklin Institute, Elsevier 2018) — are all derived analytically and validated through MATLAB-based numerical simulation. At Intel, ANOVA simulation characterized timing variation across process-voltage-temperature corners for Xeon SoC clock sign-off using Synopsys Fusion Compiler and ICC II. As Assistant Professor at IUT, the Numerical Methods and Simulation Lab course was delivered with hands-on MATLAB exercises in root-finding, interpolation, ODE solvers, and curve fitting.

  • Beneficiaries: Simulation engineers, hardware timing teams, and engineering students
  • Outcome: MATLAB-validated analytical baselines and ANOVA-verified timing sign-off workflows
  • Metric: IEEE TNS + J. Franklin Institute + Intel ANOVA + IUT Numerical Methods Lab

Neuromorphic computing & spiking neural networks

Four-plus years of research in biologically inspired computing: spiking neural network architectures with Hebbian learning rules for low-power spectrum sensing and signal demodulation, published at IEEE ICC 2024 (two papers) and submitted to IEEE GLOBECOM 2024. FPGA realization of SNN models for opportunistic spectrum access was a completed course project (UMBC, 2022), and SNN High-Level Synthesis was carried out under ONR funding as a Graduate Research Assistant. Deployment targets include CPU, GPU, Raspberry Pi, and other resource-constrained edge devices.

  • Beneficiaries: Neuromorphic hardware researchers, edge-AI engineers, and IoT/sensor network designers
  • Outcome: Energy-efficient SNN detectors and demodulators verified on FPGA and edge hardware targets
  • Metric: 4+ years neuromorphic research + IEEE ICC 2024 (×2) + GLOBECOM 2024 + ONR-funded SNN HLS

Power systems & renewable energy research

Grid-connected renewable energy and power-quality research produced two Elsevier journal publications: lead-lag susceptance control for FSIG wind generators in the Journal of The Franklin Institute (vol. 355, no. 1, 2018) and optimal UPFC-based damping for low-frequency oscillations in a single-machine infinite-bus system published in ISA Transactions. A companion IEEE R10-HTC 2017 conference paper addressed single-phase switched-capacitor AC-DC converter design for improved power quality. Power electronics and circuit lab supervision at IUT reinforced these concepts in hands-on undergraduate settings.

  • Beneficiaries: Power systems engineers, renewable energy researchers, and grid stability teams
  • Outcome: Validated lead-lag and UPFC control frameworks for wind and SMIB power system stability
  • Metric: J. Franklin Institute + ISA Transactions (Elsevier) + IEEE R10-HTC 2017

Industry Collaboration

Partnerships and joint execution
University of Maryland Baltimore County Meta Platforms (Reality Labs) Intel Corporation Lasarrus Clinic & Research Center Islamic University of Technology Kyung Hee University

From Ph.D. research to IEEE venues

Bio-inspired spectral-temporal modeling for cognitive radio matured from simulation-based dissertation work into an IEEE TCCN archival journal paper (vol. 10, no. 2, April 2024, doi: 10.1109/TCCN.2023.3342428). Parallel SNN and federated detector threads—funded by NSF and ONR—produced two accepted IEEE ICC 2024 papers and two GLOBECOM 2024 submissions, demonstrating a full pipeline from idea to reproducible, peer-reviewed baseline.

Cognitive Radio SNN Federated Learning IEEE TCCN ICC GLOBECOM

Industry internships → production hardware practice

Three consecutive industry rotations sharpened RTL-to-silicon discipline: Xeon SoC high-speed clock distribution (skew, jitter, power, ANOVA) at Intel using Synopsys Fusion Compiler and ICC II (2022–2023); FPGA-based WearME prototype for COPD patients—including ADC/DAC interfaces, PLL design, and FDA-compliant documentation—at Lasarrus Clinic (2023–2024); and LCoS laser-controller RTL/HLS for AR/VR true-color micro-display with SWaP-C analysis and post-silicon validation at Meta Reality Labs (Summer 2024).

ASIC FPGA RTL HLS Intel Meta Lasarrus SWaP-C

Radiation-hardened silicon at Kyung Hee University

Graduate research (2013–2015) at the CSA & VLSI Lab produced three tape-out chips: TID effect on SRAM standby power (28 nm FD-SOI), radiation effect in combinational circuits (28 nm FD-SOI), and robust flip-flop design to mitigate single-event upset (130 nm HCOMS9SOI). The SRAM work was published in IEEE Transactions on Nuclear Science (vol. 62.3, 2015: 1349–1356) and verified at the Korea Institute of Radiological & Medical Sciences under nuclear radiation conditions.

SRAM Flip-Flop Radiation Hardening Tape-out IEEE Nuclear Science Cadence

Teaching career across two continents

Four-and-a-half years on faculty at Islamic University of Technology (Lecturer 2016–2019, Assistant Professor 2019–2021) delivering VLSI circuits, semiconductor devices, numerical methods, and six laboratory courses to undergraduate engineering cohorts in Bangladesh. Continued at UMBC since 2021 as a Graduate Teaching Assistant across five graduate courses — Advanced Computer Architecture (CMPE/CMSC 611), Advanced Machine Learning (CMPE 678), Digital Image Processing (ENEE 612), Programmable Logic Devices (CMPE 415), and Circuit Theory (CMPE 306) — building a 10+ year record of structured instruction on two continents.

Teaching VLSI UMBC IUT Mentorship Graduate TA Circuit Theory Machine Learning

Funding, publishing & service

Federal grants, IEEE venues, and peer review.
NSF / ONR

Federally funded research threads

Cross-medium ML modulation for multipath edge communication funded by NSF (BINDNET PyTorch framework, accepted at IEEE ICC 2024). Dynamic FPGA partial reconfiguration and SNN High-Level Synthesis funded by ONR (accepted in both an IEEE Transaction and an IEEE conference). Both threads demonstrate grant-to-publication execution from a Ph.D. GRA role.

Published

IEEE archival publication stream

Eleven peer-reviewed publications spanning IEEE TCCN, IEEE Transactions on Nuclear Science, Journal of The Franklin Institute (Elsevier), ISA Transactions (Elsevier), Journal of Electronic Materials (Springer), IEEE ICC, IEEE ISCAS, IEEE GLOBECOM, and IEEE R10-HTC — with ongoing submissions in cognitive radio, SNN-based detectors, and optoacoustic communications.

Service

Peer review & academic service

Technical reviewer for IEEE Transactions on Nuclear Science, IEEE Transactions on Sustainable Energy, International Journal of Electrical Power & Energy Systems, IEEE Sensors Journal, and International Journal of Computers and Applications — contributing quality control to five archival venues aligned with hardware, energy, and communications research.

Public profiles

Scholar citations, professional network, and open-source code.
Google Scholar Open Scholar

Citation profile & publications index

Authoritative Google Scholar profile for Md Mehedi Hassan Galib — citation counts, full venue list covering IEEE TCCN, Nuclear Science, Franklin Institute, ICC, ISCAS, GLOBECOM, and more. Quick entry point alongside the Publications page for collaborators verifying research output.

LinkedIn Open LinkedIn

Professional network & career timeline

Full career timeline: Meta Reality Labs (AR/VR FPGA intern), Intel (Xeon SoC structural design intern), Lasarrus Clinic (WearME FPGA intern), UMBC Graduate Assistant, Islamic University of Technology (Assistant Professor & Lecturer), and Kyung Hee University (Graduate Research Assistant). Preferred first-contact channel for industry collaborators.

GitHub Open GitHub

Code, coursework artifacts & prototypes

Repositories spanning spectrum ML experiments, spiking neural network coursework, FPGA capstone projects, TCN benchmarks, and hardware/ML co-design exercises from UMBC and beyond. Open-source artifacts aligned with reproducibility goals in cognitive radio and neuromorphic computing research.

ORCID Open ORCID

Persistent researcher identity

ORCID iD 0000-0002-5683-7016 provides a persistent, unambiguous identifier linking all publications, affiliations, and funding records for Md Mehedi Hassan Galib across publisher platforms and grant databases.

Impact Timeline

Archival research, industry practice, and teaching—in one through-line.
  1. Root: B.Sc. EEE at Islamic University of Technology (2012, CGPA 3.98) followed by M.Sc. in Electronics & Radio Engineering at Kyung Hee University, South Korea (2015, CGPA 4.1/4.3). Tape-out chip research in radiation-hardened SRAM and flip-flop circuits using 28 nm FD-SOI and 130 nm HCOMS9SOI technologies — verified under nuclear radiation conditions.
  2. Teach: Four-and-a-half years as faculty at IUT — Lecturer (2016–2019) then Assistant Professor (2019–2021) — covering VLSI circuits, semiconductor devices, digital electronics, and microprocessor lab courses. UMBC graduate TAships since 2021 across Advanced Computer Architecture, Machine Learning, Digital Image Processing, and Circuit Theory.
  3. Research: Ph.D. in Computer Engineering at UMBC (2021–2025, CGPA 3.97): bio-inspired spectral-temporal models for cognitive radio, spiking neural network-based spectrum detectors, and federated learning approaches for opportunistic spectrum access — NSF and ONR funded. Published in IEEE TCCN (2024), ICC (2024), and GLOBECOM (2024).
  4. Ship: Three industry rotations reinforced RTL-to-silicon discipline: Xeon SoC clock distribution at Intel (2022–2023), WearME FPGA prototype for COPD patients at Lasarrus Clinic (2023–2024), and LCoS laser-controller RTL/HLS for AR/VR micro-display at Meta Reality Labs (Summer 2024) — spanning SWaP-C analysis, verification reviews, and post-silicon validation.
  5. Publish: Eleven peer-reviewed publications across IEEE TCCN, IEEE Transactions on Nuclear Science, Journal of The Franklin Institute (Elsevier), ISA Transactions (Elsevier), Journal of Electronic Materials (Springer), IEEE ICC, IEEE ISCAS, IEEE GLOBECOM, and IEEE R10-HTC. Reviewer for five IEEE and Elsevier archival journals.